--
-- Synopsys
-- Vhdl wrapper for top level design, written on Tue Nov 19 16:14:57 2024
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity wrapper_for_Top is
   port (
      Clk : in std_logic;
      Key_in : in std_logic_vector(5 downto 0);
      USART1_TX : in std_logic;
      USART1_RX : out std_logic;
      USART3_TX : in std_logic;
      USART3_RX : out std_logic;
      FSMC_CLK : in std_logic;
      FSMC_NE : in std_logic;
      FSMC_NOE : in std_logic;
      FSMC_NWE : in std_logic;
      FSMC_NWAIT : in std_logic;
      FSMC_NADV : in std_logic;
      FSMC_AD : in std_logic_vector(15 downto 0);
      RX1 : in std_logic;
      TX1 : out std_logic;
      RX2 : in std_logic;
      TX2 : out std_logic;
      RX3 : in std_logic;
      TX3 : out std_logic;
      RX4 : in std_logic;
      TX4 : out std_logic;
      RX6 : in std_logic;
      TX6 : out std_logic;
      PulseOut : out std_logic_vector(1 downto 0);
      LaserLed : out std_logic;
      Cross_EN : out std_logic;
      TB_in : in std_logic;
      EN1 : out std_logic;
      EN2 : out std_logic;
      EN3 : out std_logic;
      EN4 : out std_logic;
      PulseOut_48 : out std_logic;
      PulseOut_49 : out std_logic;
      PulseOutCheck : in std_logic;
      test1535_pin : out std_logic;
      LED : out std_logic_vector(1 downto 0)
   );
end wrapper_for_Top;

architecture top_arch of wrapper_for_Top is

component Top
 port (
   Clk : in std_logic;
   Key_in : in std_logic_vector (5 downto 0);
   USART1_TX : in std_logic;
   USART1_RX : out std_logic;
   USART3_TX : in std_logic;
   USART3_RX : out std_logic;
   FSMC_CLK : in std_logic;
   FSMC_NE : in std_logic;
   FSMC_NOE : in std_logic;
   FSMC_NWE : in std_logic;
   FSMC_NWAIT : in std_logic;
   FSMC_NADV : in std_logic;
   FSMC_AD : inout std_logic_vector (15 downto 0);
   RX1 : in std_logic;
   TX1 : out std_logic;
   RX2 : in std_logic;
   TX2 : out std_logic;
   RX3 : in std_logic;
   TX3 : out std_logic;
   RX4 : in std_logic;
   TX4 : out std_logic;
   RX6 : in std_logic;
   TX6 : out std_logic;
   PulseOut : out std_logic_vector (1 downto 0);
   LaserLed : out std_logic;
   Cross_EN : out std_logic;
   TB_in : in std_logic;
   EN1 : out std_logic;
   EN2 : out std_logic;
   EN3 : out std_logic;
   EN4 : out std_logic;
   PulseOut_48 : out std_logic;
   PulseOut_49 : out std_logic;
   PulseOutCheck : in std_logic;
   test1535_pin : out std_logic;
   LED : out std_logic_vector (1 downto 0)
 );
end component;

signal tmp_Clk : std_logic;
signal tmp_Key_in : std_logic_vector (5 downto 0);
signal tmp_USART1_TX : std_logic;
signal tmp_USART1_RX : std_logic;
signal tmp_USART3_TX : std_logic;
signal tmp_USART3_RX : std_logic;
signal tmp_FSMC_CLK : std_logic;
signal tmp_FSMC_NE : std_logic;
signal tmp_FSMC_NOE : std_logic;
signal tmp_FSMC_NWE : std_logic;
signal tmp_FSMC_NWAIT : std_logic;
signal tmp_FSMC_NADV : std_logic;
signal tmp_FSMC_AD : std_logic_vector (15 downto 0);
signal tmp_RX1 : std_logic;
signal tmp_TX1 : std_logic;
signal tmp_RX2 : std_logic;
signal tmp_TX2 : std_logic;
signal tmp_RX3 : std_logic;
signal tmp_TX3 : std_logic;
signal tmp_RX4 : std_logic;
signal tmp_TX4 : std_logic;
signal tmp_RX6 : std_logic;
signal tmp_TX6 : std_logic;
signal tmp_PulseOut : std_logic_vector (1 downto 0);
signal tmp_LaserLed : std_logic;
signal tmp_Cross_EN : std_logic;
signal tmp_TB_in : std_logic;
signal tmp_EN1 : std_logic;
signal tmp_EN2 : std_logic;
signal tmp_EN3 : std_logic;
signal tmp_EN4 : std_logic;
signal tmp_PulseOut_48 : std_logic;
signal tmp_PulseOut_49 : std_logic;
signal tmp_PulseOutCheck : std_logic;
signal tmp_test1535_pin : std_logic;
signal tmp_LED : std_logic_vector (1 downto 0);

begin

tmp_Clk <= Clk;

tmp_Key_in <= Key_in;

tmp_USART1_TX <= USART1_TX;

USART1_RX <= tmp_USART1_RX;

tmp_USART3_TX <= USART3_TX;

USART3_RX <= tmp_USART3_RX;

tmp_FSMC_CLK <= FSMC_CLK;

tmp_FSMC_NE <= FSMC_NE;

tmp_FSMC_NOE <= FSMC_NOE;

tmp_FSMC_NWE <= FSMC_NWE;

tmp_FSMC_NWAIT <= FSMC_NWAIT;

tmp_FSMC_NADV <= FSMC_NADV;

tmp_FSMC_AD <= FSMC_AD;

tmp_RX1 <= RX1;

TX1 <= tmp_TX1;

tmp_RX2 <= RX2;

TX2 <= tmp_TX2;

tmp_RX3 <= RX3;

TX3 <= tmp_TX3;

tmp_RX4 <= RX4;

TX4 <= tmp_TX4;

tmp_RX6 <= RX6;

TX6 <= tmp_TX6;

PulseOut <= tmp_PulseOut;

LaserLed <= tmp_LaserLed;

Cross_EN <= tmp_Cross_EN;

tmp_TB_in <= TB_in;

EN1 <= tmp_EN1;

EN2 <= tmp_EN2;

EN3 <= tmp_EN3;

EN4 <= tmp_EN4;

PulseOut_48 <= tmp_PulseOut_48;

PulseOut_49 <= tmp_PulseOut_49;

tmp_PulseOutCheck <= PulseOutCheck;

test1535_pin <= tmp_test1535_pin;

LED <= tmp_LED;



u1:   Top port map (
		Clk => tmp_Clk,
		Key_in => tmp_Key_in,
		USART1_TX => tmp_USART1_TX,
		USART1_RX => tmp_USART1_RX,
		USART3_TX => tmp_USART3_TX,
		USART3_RX => tmp_USART3_RX,
		FSMC_CLK => tmp_FSMC_CLK,
		FSMC_NE => tmp_FSMC_NE,
		FSMC_NOE => tmp_FSMC_NOE,
		FSMC_NWE => tmp_FSMC_NWE,
		FSMC_NWAIT => tmp_FSMC_NWAIT,
		FSMC_NADV => tmp_FSMC_NADV,
		FSMC_AD => tmp_FSMC_AD,
		RX1 => tmp_RX1,
		TX1 => tmp_TX1,
		RX2 => tmp_RX2,
		TX2 => tmp_TX2,
		RX3 => tmp_RX3,
		TX3 => tmp_TX3,
		RX4 => tmp_RX4,
		TX4 => tmp_TX4,
		RX6 => tmp_RX6,
		TX6 => tmp_TX6,
		PulseOut => tmp_PulseOut,
		LaserLed => tmp_LaserLed,
		Cross_EN => tmp_Cross_EN,
		TB_in => tmp_TB_in,
		EN1 => tmp_EN1,
		EN2 => tmp_EN2,
		EN3 => tmp_EN3,
		EN4 => tmp_EN4,
		PulseOut_48 => tmp_PulseOut_48,
		PulseOut_49 => tmp_PulseOut_49,
		PulseOutCheck => tmp_PulseOutCheck,
		test1535_pin => tmp_test1535_pin,
		LED => tmp_LED
       );
end top_arch;
